An Efficient Way from UML Behavior Models to VLSI-Architectures

Vortrag auf der Embedded World Konferenz 2010
Autoren: P. Partsch, M. Holzer, T. Greiner, F. Schumacher, F. Kesel
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Abstract:
Using Unified Modeling Language (UML) as system design language for digital hardware
systems could lead to several improvements in the overall design process. By increasing the
abstraction level, one of the major benefits of the usage of UML is a better ability for
parameterization and reuse of parts of the Very Large Scale Integration (VLSI)-Design, which
is commonly structured in so called Intellectual Property (IP)-Modules.
By using UML as system design language, several obstacles must be overcome. One of
them is the semantic variations, i.e. in UML the same aspect can be modeled with different
notations. We solve this disadvantage by presenting an automatic code generation
approach, which uses an UML input model and combines different notations of UML
(Composite Structure Diagram, Activity and State Diagrams). Therefore, several well
established techniques and tools from the Model Driven Software Development (MDSD)
such as meta-models and multistage model-to-model transformations to achieve code
generation are utilized.
The first step in our approach uses the suitable meta-model for the selected diagram types
and a platform independent (PI) model-to-model (M2M) transformation, which leads to a
clear semantic. As a result the determination of the behavior of the modeled data processing
IP-Block is achieved.
Within this step the UML input model is checked against restrictions defined in the metamodel
for the corresponding diagram type. If necessary, violations are notified to the user by
warning and error messages. For the succeeding code generation, further language specific
M2M transformations are used, which are defined by a set of generator templates. As target
languages we support SystemC and additionally VHDL. To improve the structural and
scaling aspect of the design we support hierarchical state machines with parallel subregions.
In addition to actual generated architecture source code files, we also generate a test bench
for functional test proposal, which is optionally equipped with test and verification patterns
defined in the UML model.
The described generator workflow uses the open source framework openArchitectureWare
(oAW) and is integrated into an independent Electronic Design Automation (EDA)-Tool with
Graphical User Interface (GUI).